Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or

equivalent practical experience.

• Experience in ASIC development with Verilog/SystemVerilog, VHDL.

• Experience in logic design and debug.

• Experience with ASIC design verification, synthesis, timing/power analysis, or DFT.

Preferred qualifications:

• Knowledge of high performance and low power design techniques.

• Knowledge of SOC architecture.

• Knowledge of assertion-based formal verification.

• Knowledge in one of these areas: PCIe, DDR, AXI, ARM processors family.

• Proficiency with a scripting language like Tcl, Python or Perl.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As part of our server chip design team, you will use the ASIC design experience to be part of a team that develops the ASIC SoC and SoC IP’s from POR to Production. You will create SoC Level micro architecture definitions, RTL coding and all RTL quality checks. You will also have the opportunity to contribute to Design flow and Methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis DFT etc. You will develop/define design options for performance, power and area.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

• Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.

• Perform RTL development (i.e., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.

• Develop a flow for CDC/RDC and assimilate hierarchically in the organization and Write SDC and Run synthesis.Be able to debug timing/power and support ASIC silicon bring-up.

• Participate in test plan and coverage analysis of the block and SOC-level verification.

• Communicate and work with multi-disciplined and multi-site teams.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.