Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.

• Experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs.

• Experience creating and using verification components and environments in standard verification methodology.

Preferred qualifications:

• Master’s degree in Electrical Engineering or Computer Science.

• Experience with CPU implementation, assembly language, or compute System on a Chip (SOC).

• Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Junior CPU Design Verification Engineer, you will work as part of a Research and Development team, and will include build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will use your design and verification expertise to verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform verification. You'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. In addition, you will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

• Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.

• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.

• Identify and write all types of coverage measures for stimulus and corner-cases.

• Debug tests with design engineers to deliver functionally correct design blocks.

• Close coverage measures to identify verification holes and to show progress towards tape-out.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.